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freescale semiconductor data sheet: advance information document number: mcf54455 rev. 2, 05/2008 ? freescale semiconductor, inc., 2008. all rights reserved. this document contains information on a new product. specifications and information herein are subject to change without notice. mcf54455 mapbga?256 17mm x 17mm tepbga?360 23mm x 23mm features ?version 4 coldfire ? core with mmu and emac ? up to 410 dhrystone 2.1 mips @ 266 mhz ? 16-kbytes instruction cache and 16-kbytes data cache ? 32-kbytes internal sram ? support for booting from spi-compatible flash, eeprom, and fram devices ? crossbar switch technology (x bs) for concurrent access to peripherals or ram from multiple bus masters ? 16-channel dma controller ? 16-bit 133-mhz ddr/mobile-ddr/ddr2 controller ? usb 2.0 on-the-go controller with ulpi support ? 32-bit pci controller @ 66mhz ? ata/atapi controller ? 2 10/100 ethernet macs ? coprocessor for acceleration of the des, 3des, aes, md5, and sha-1 algorithms ? random number generator ? synchronous serial interface (ssi) ? 4 periodic interrupt timers (pit) ? 4 32-bit timers with dma support ? dma-supported serial pe ripheral interface (dspi) ? 3 uarts ?i 2 c bus interface mcf5445 x coldfire ? microprocessor data sheet
mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 2 table of contents 1 mcf5445 x family comparison . . . . . . . . . . . . . . . . . . . . . . . .4 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 analog power filtering . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 oscillator power filtering . . . . . . . . . . . . . . . . . . . . . . . .6 3.3 supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . .6 3.3.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . .7 3.3.2 power-down sequence . . . . . . . . . . . . . . . . . . . .7 4 pin assignments and reset states . . . . . . . . . . . . . . . . . . . . .7 4.1 signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.2 pinout?256 mapbga . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3 pinout?360 tepbga. . . . . . . . . . . . . . . . . . . . . . . . . .16 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .17 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .18 5.3 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.4 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .19 5.5 clocktiming specifications . . . . . . . . . . . . . . . . . . . . . .20 5.6 reset timing specifications . . . . . . . . . . . . . . . . . . . . .22 5.7 flexbus timing specifications . . . . . . . . . . . . . . . . . . .23 5.8 sdram ac timing characteristics. . . . . . . . . . . . . . . .25 5.9 pci bus timing specifications . . . . . . . . . . . . . . . . . . 27 5.9.1 overshoot and undershoot . . . . . . . . . . . . . . . 28 5.10 ulpi timing specifications . . . . . . . . . . . . . . . . . . . . . 29 5.11 ssi timing specifications . . . . . . . . . . . . . . . . . . . . . . 30 5.12 i 2 c timing specifications . . . . . . . . . . . . . . . . . . . . . . 32 5.13 fast ethernet timing specifications . . . . . . . . . . . . . . 33 5.13.1 receive signal timing spec ifications . . . . . . . 33 5.13.2 transmit signal timing specifications . . . . . . . 34 5.13.3 asynchronous input signal timing specifications34 5.13.4 mii serial management timing specifications . 35 5.14 32-bit timer module timing specifications . . . . . . . . . 35 5.15 ata interface timing specifications. . . . . . . . . . . . . . . 36 5.16 dspi timing specifications . . . . . . . . . . . . . . . . . . . . . 36 5.17 sbf timing specifications. . . . . . . . . . . . . . . . . . . . . . 38 5.18 general purpose i/o timing s pecifications. . . . . . . . . 39 5.19 jtag and boundary scan timing . . . . . . . . . . . . . . . . 40 5.20 debug ac timing specifications . . . . . . . . . . . . . . . . . 42 6 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 3 figure 1. mcf54455 block diagram version 4 coldfire core legend 2 intcs dspi eport 3 uarts i 2 c watchdog 4 dma rtc ata ? advanced technology attachment controller bdm ? background debug module cau ? cryptography acceleration unit dspi ? dma serial peripheral interface edma ? enhanced direct memory access emac ? enchance multiply-accumulate unit eport ? edge port module fec ? fast ethernet controller gpio ? general purpose input/output module i 2 c ? inter-intergrated circuit intc ? interrupt controller jtag ? joint test action group interface mmu ? memory management unit pci ? peripheral component interconnect pit ? programmable interrupt timers pll ? phase locked loop module rng ? random number generator rtc ? real time clock ssi ? synchronous serial interface usb otg ? universal serial bus on-the-go controller mcf54455 emac 2 fecs crossbar switch (xbs) 32k sram peripheral bridge cau 16k instruction cache 16k data cache timers bdm ata sdram controller flexbus edma usb otg 4 pits ssi rng gpio mmu hardware divide oscillator pll jtag pci serial boot
mcf5445x coldfire ? microprocessor data sheet, rev. 2 mcf5445x family comparison freescale semiconductor 4 1 mcf5445 x family comparison the following table compares the various device derivatives available within the mcf5445 x family. table 1. mcf5445 x family configurations module mcf54450 MCF54451 mcf544 52 mcf54453 mcf54454 mcf54455 coldfire version 4 core with emac (enhanced multiply-accumulate unit) ?????? core (system) clock up to 240 mhz up to 266 mhz peripheral bus clock (core clock 2) up to 120 mhz up to 133 mhz external bus clock (core clock 4) up to 60 mhz up to 66 mhz performance (dhrystone/2.1 mips) up to 370 up to 410 independent data/instruction cache 16 kbytes each static ram (sram) 32 kbytes pci controller ?????? cryptography acceleration unit (cau) ? ? ? ? ? ? ata controller ???? ? ? ddr sdram controller ?????? flexbus external interface ?????? usb 2.0 on-the-go ?????? utmi+ low pin interface (ulpi) ?????? synchronous serial interface (ssi) ?????? fast ethernet controller (fec) 112222 uarts 333333 i 2 c ?????? dspi ?????? real time clock ?????? 32-bit dma timers 444444 watchdog timer (wdt) ?????? periodic interrupt timers (pit) 444444 edge port module (eport) ?????? interrupt controllers (intc) 222222 16-channel direct memory access (dma)?????? general purpose i/o module (gpio)?????? jtag ? ieee ? 1149.1 test access port ?????? package 256 mapbga 360 tepbga
ordering information mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 5 2 ordering information 3 hardware design considerations 3.1 analog power filtering to further enhance noise isolation, an external filter is strongly recommended for the analog v dd pins (vdd_a_pll, vdd_rtc). the filter shown in figure 2 should be connected between the board iv dd and the analog pins. the resistor and capacitors should be placed as cl ose to the dedicated analog v dd pin as possible. the 10- resistor in the given filter is required. do not implement the filter circuit using only capacitors. the analog power pins draw very little current. concerns regarding voltage loss across the 10-ohm resistor are not valid. figure 2. system analog v dd power filter table 2. orderable part numbers freescale part number description package speed temperature mcf54450vm180 mcf54450 microprocessor 256 mapbga 180 mhz 0 to +70 c mcf54450vm240 240 mhz MCF54451cvm180 MCF54451 microprocessor 180 mhz ?40 to +85 c MCF54451vm240 240 mhz 0 to +70 c mcf54452cvr200 mcf54452 microprocessor 360 tepbga 200 mhz ?40 to +85 c mcf54452vr266 266 mhz 0 to +70 c mcf54453cvr200 mcf54453 microprocessor 200 mhz ?40 to +85 c mcf54453vr266 266 mhz 0 to +70 c mcf54454cvr200 mcf54454 microprocessor 200 mhz ?40 to +85 c mcf54454vr266 266 mhz 0 to +70 c mcf54455cvr200 mcf54455 microprocessor 200 mhz ?40 to +85 c mcf54455vr266 266 mhz 0 to +70 c board iv dd 10 0.1 f analog v dd pin 10 f gnd
mcf5445x coldfire ? microprocessor data sheet, rev. 2 hardware design considerations freescale semiconductor 6 3.2 oscillator power filtering figure 3 shows an example for isolating the oscillator power supply from the i/o supply (evdd) and ground. figure 3. oscillator power filter 3.3 supply voltage sequencing figure 4 shows situations in sequencing the i/o v dd (ev dd ), sdram v dd (sdv dd ), pll v dd (pv dd ), and internal logic/core v dd (iv dd ). figure 4. supply voltage sequencing and separation cautions the relationship between sdv dd and ev dd is non-critical during power-up and power-down sequences. sdv dd (2.5v or 1.8v) and ev dd are specified relative to iv dd . vdd_osc 10 0.1 f evdd pin 1 f gnd vss_osc 100 mhz ev dd (3.3v) iv dd , pv dd time 3.3v 1.5v 0 dc power supply voltage notes: 1 input voltage must not be greater than the supply voltage (ev dd , sdv dd , iv dd , or pv dd ) by more than 0.5v at any time, including during power-up. 2 use 50 v/millisecond or slower rise time for all supplies. 2.5v supplies stable sdv dd (2.5v ? ddr) 1.8v sdv dd (1.8v ? ddr2)
pin assignments and reset states mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 7 3.3.1 power-up sequence if ev dd /sdv dd are powered up with the iv dd at 0 v, the sense circuits in the i/o pa ds cause all pad output drivers connected to the ev dd /sdv dd to be in a high impedance state. there is no limit on how long after ev dd /sdv dd powers up before iv dd must power up. the rise times on the power supplies should be slower than 50 v/millisecond to avoid turning on the internal esd protection clamp diodes. 3.3.2 power-down sequence if iv dd /pv dd are powered down first, sense circuits in the i/o pads cause all output driv ers to be in a high impedance state. there is no limit on how long after iv dd and pv dd power down before ev dd or sdv dd must power down. there are no requirements for the fall times of the power supplies. 4 pin assignments and reset states 4.1 signal multiplexing the following table lists all the mcf5445 x pins grouped by function. the dir column is the direction for the primary function of the pin only. refer to section 4, ?pin assignments and reset states ,? for package diagrams. for a more detailed discussion of the mcf5445 x signals, consult the mcf54455 reference manual (mcf54455rm). note in this table and throughout this document, a single signal within a group is designated without square brackets (i.e., fb_ad23), while designations for multiple signals within a group use brackets (i.e., fb_ad[23:21]) and is meant to include all signals within the two bracketed numbers when these num bers are separated by a colon. note the primary functionality of a pin is not necessarily its default functionality. most pins that are muxed with gpio default to their gpio functionality. see table 3 for a list of the exceptions. table 3. special-case default signal functionality pin 256 mapbga 360 tepbga fb_ad[31:0] fb_ad[31:0] except wh en serial boot selects 0-bit boot port size. fb_be/bwe [3:0] fb_be/bwe [3:0] fb_cs [3:1] fb_cs [3:1] fb_oe fb_oe fb_r/w fb_r/w fb_ta fb_ta fb_ts fb_ts
mcf5445x coldfire ? microprocessor data sheet, rev. 2 pin assignments and reset states freescale semiconductor 8 pci_gnt [3:0] gpio pci_gnt [3:0] pci_req [3:0] gpio pci_req [3:0] irq1 gpio pci_inta and configured as an agent. ata_reset gpio ata reset table 4. mcf5445 x signal information and muxing signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga reset reset ? ? ? u i evdd l4 y18 rstout ? ? ? ? o evdd m15 b17 clock extal/pci_clk ? ? ? ? i evdd m16 a16 xtal ? ? ? u 3 o evdd l16 a17 mode selection bootmod[1:0] ? ? ? ? i evdd m5, m7 ab17, ab21 flexbus fb_ad[31:24] pfbadh[7:0] 4 fb_d[31:24] ? ? i/o evdd a14, a13, d12, c12, b12, a12, d11, c11 j2, k4, j1, k1?3, l1, l4 fb_ad[23:16] pfbadmh[7:0] 4 fb_d[23:16] ? ? i/o evdd b11, a11, d10, c10, b10, a10, d9, c9 l2, l3, m1?4, n1?2 fb_ad[15:8] pfbadml[7:0] 4 fb_d[15:8] ? ? i/o evdd b9, a9, d8, c8, b8, a8, d7, c7 p1?2, r1?3, p4, t1?2 fb_ad[7:0] pfbadl[7:0] 4 fb_d[7:0] ? ? i/o evdd b7, a7, d6, c6, b6, a6, d5, c5 t3?4, u1?3, v1?2, w1 fb_be/bwe [3:2] pbe[3:2] fb_tsiz[1:0] ? ? o evdd b5, a5 y1, w2 fb_be/bwe [1:0] pbe[1:0] ? ? ? o evdd b4, a4 w3, y2 fb_clk ? ? ? ? o evdd b13 j3 fb_cs [3:1] pcs[3:1] ? ? ? o evdd c2, d4, c3 w5, aa4, ab3 fb_cs0 ?? ? ? o evdd c4 y4 fb_oe pfbctl3 ? ? ? o evdd a2 aa1 fb_r/w pfbctl2 ? ? ? o evdd b2 aa3 fb_ta pfbctl1 ? ? u i evdd b1 ab2 table 3. special-case default signal functionality (continued) pin 256 mapbga 360 tepbga
pin assignments and reset states mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 9 fb_ts pfbctl0 fb_ale fb_tbst ? o evdd a3 y3 pci controller 5 pci_ad[31:24] ? fb_a[31:24] ? ? i/o evdd ? c11, d11, a10, b10, j4, g2, g3, f1 pci_ad[23:0] ? fb_a[23:0] ? ? i/o evdd k14?13, j15?13, h13?15, g15?13, f14?13, e15?13, d16, b16, c15, b15, c14, d15, c16, d14 d12, c12, b12, a11, b11, b9, d9, d10, a8, b8, a5, b5, a4, a3, b3, d4, d3, e3?e1, f3, c2, d2, c1 pci_cbe [3:0] ? ? ? ? i/o evdd ? g4, e4, d1, b1 pci_devsel ?? ? ? o evdd ? f2 pci_frame ?? ? ? i/o evdd ? b2 pci_gnt3 ppci7 ata_dmack ? ? o evdd ? b7 pci_gnt [2:1] ppci[6:5] ? ? ? o evdd ? c8, c9 pci_gnt0 / pci_extreq ppci4 ? ? ? o evdd ? a9 pci_idsel ? ? ? ? i evdd ? d5 pci_irdy ?? ? ? i/o evdd ? c3 pci_par ? ? ? ? i/o evdd ? c4 pci_perr ?? ? ? i/o evdd ? b4 pci_req3 ppci3 ata_intrq ? ? i evdd ? c7 pci_req [2:1] ppci[2:1] ? ? ? i evdd ? d7, c5 pci_req0 / pci_extgnt ppci0 ? ? ? i evdd ? a2 pci_rst ?? ? ? o evdd ? b6 pci_serr ?? ? ? i/o evdd ? a6 pci_stop ?? ? ? i/o evdd ? a7 pci_trdy ?? ? ? i/o evdd ? c10 sdram controller sd_a[13:0] ? ? ? ? o sdvdd r1, p1, n2, p2, r2, t2, m4, n3, p3, r3, t3, t4, r4, n4 v22, u20?22, t19?22, r20?22, n19, p20?21 sd_ba[1:0] ? ? ? ? o sdvdd p4, t5 p22, p19 sd_cas ?? ? ? o sdvdd t6 l19 sd_cke ? ? ? ? o sdvdd n5 n22 table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
mcf5445x coldfire ? microprocessor data sheet, rev. 2 pin assignments and reset states freescale semiconductor 10 sd_clk ? ? ? ? o sdvdd t9 l22 sd_clk ?? ? ? o sdvdd t8 m22 sd_cs [1:0] ? ? ? ? o sdvdd p6, r6 l20, m20 sd_d[31:16] ? ? ? ? i/o sdvdd n6, t7, n7, p7, r7, r8, p8, n8, n9, t10, r10, p10, n10, t11, r11, p11 l21, k22, k21, k20, j20, j19, j21, j22, h20, g22, g21, g20, g19, f22, f21, f20 sd_dm[3:2] ? ? ? ? o sdvdd p9, n12 h21, e21 sd_dqs[3:2] ? ? ? ? o sdvdd r9, n11 h22, e22 sd_ras ?? ? ? o sdvdd p5 n21 sd_vref ? ? ? ? i sdvdd m8 m21 sd_we ?? ? ? o sdvdd r5 n20 external interrupts port 6 irq7 pirq7 ? ? ? i evdd l1 abb13 irq4 pirq4 ? ssi_clkin ? i evdd l2 abb13 irq3 pirq3 ? ? ? i evdd l3 ab14 irq1 pirq1 pci_inta ? ? i evdd f15 c6 fec0 fec0_mdc pfeci2c3 ? ? ? o evdd f3 ab8 fec0_mdio pfeci2c2 ? ? ? i/o evdd f2 y7 fec0_col pfec0h4 ? ulpi_data7 ? i evdd e1 ab7 fec0_crs pfec0h0 ? ulpi_data6 ? i evdd f1 aa7 fec0_rxclk pfec0h3 ? ulpi_data1 ? i evdd g1 aa8 fec0_rxdv pfec0h2 fec0_rmii_ crs_dv ? ? i evdd g2 y8 fec0_rxd[3:2] pfec0l[3:2] ? ulpi_data[5:4] ? i evdd g3, g4 ab9, y9 fec0_rxd1 pfec0l1 fec0_rmii_rxd1 ? ? i evdd h1 w9 fec0_rxd0 pfec0h1 fec0_rmii_rxd0 ? ? i evdd h2 ab10 fec0_rxer pfec0l0 fec0_rmii_rxer ? ? i evdd h3 aa10 fec0_txclk pfec0h7 fec0_rmii_ ref_clk ? ? i evdd h4 y10 fec0_txd[3:2] pfec0l[7:6] ? ulpi_data[3:2] ? o evdd j1, j2 w10, ab11 fec0_txd1 pfec0l5 fec0_rmii_txd1 ? ? o evdd j3 aa11 table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
pin assignments and reset states mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 11 fec0_txd0 pfec0h5 fec0_rmii_txd0 ? ? o evdd j4 y11 fec0_txen pfec0h6 fec0_rmii_txen ? ? o evdd k1 w11 fec0_txer pfec0l4 ? ulpi_data0 ? o evdd k2 ab12 fec1 fec1_mdc pfeci2c5 ? ata _ d i o r ? o evdd ? w20 fec1_mdio pfeci2c4 ? ata _ d i ow ? i/o evdd ? y22 fec1_col pfec1h4 ? ata _ data 7 ? i evdd ? ab18 fec1_crs pfec1h0 ? ata _ data 6 ? i evdd ? aa18 fec1_rxclk pfec1h3 ? ata _ data 5 ? i evdd ? w14 fec1_rxdv pfec1h2 fec1_rmii_ crs_dv ata _ data 1 5 ? i evdd ? ab15 fec1_rxd[3:2] pfec1l[3:2] ? ata_data[4:3] ? i evdd ? aa15, y15 fec1_rxd1 pfec1l1 fec1_rmii_rxd1 ata _ data 1 4 ? i evdd ? aa17 fec1_rxd0 pfec1h1 fec1_rmii_rxd0 ata _ data 1 3 ? i evdd ? y17 fec1_rxer pfec1l0 fec1_rmii_rxer ata _ data 1 2 ? i evdd ? w17 fec1_txclk pfec1h7 fec1_rmii_ ref_clk ata _ data 1 1 ? i evdd ? ab19 fec1_txd[3:2] pfec1l[7:6] ? ata_data[2:1] ? o evdd ? y19, w18 fec1_txd1 pfec1l5 fec1_rmii_txd1 ata _ data 1 0 ? o evdd ? aa19 fec1_txd0 pfec1h5 fec1_rmii_txd0 ata _ data 9 ? o evdd ? y20 fec1_txen pfec1h6 fec1_rmii_txen ata _ data 8 ? o evdd ? aa21 fec1_txer pfec1l4 ? ata _ data 0 ? o evdd ? aa22 usb on-the-go usb_dm ? ? ? ? o usb vdd f16 a14 usb_dp ? ? ? ? o usb vdd e16 a15 usb_vbus_en pusb1 usb_pullup ulpi_nxt ? o usb vdd e5 aa2 usb_vbus_oc pusb0 ? ulpi_stp ud 7 i usb vdd b3 v4 ata ata _ b u f f e r _ e n pata h 5 ? ? ? o evdd ? y13 ata _ c s [1:0] patah[4:3] ? ? ? o evdd ? w21, w22 table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
mcf5445x coldfire ? microprocessor data sheet, rev. 2 pin assignments and reset states freescale semiconductor 12 ata_da[2:0] patah[2:0] ? ? ? o evdd ? v19?21 ata_reset pata l 2 ? ? ? o evdd ? w13 ata_dmarq pata l 1 ? ? ? i evdd ? aa14 ata _ i o r dy pata l 0 ? ? ? i evdd ? y14 real time clock extal32k ? ? ? ? i evdd j16 a13 xtal32k ? ? ? ? o evdd h16 a12 ssi ssi_mclk pssi4 ? ? ? o evdd t13 d20 ssi_bclk pssi3 u1cts ? ? i/o evdd r13 e19 ssi_fs pssi2 u1rts ? ? i/o evdd p12 e20 ssi_rxd pssi1 u1rxd ? ud i evdd t12 d21 ssi_txd pssi0 u1txd ? ud o evdd r12 d22 i 2 c i2c_scl pfeci2c1 ? u2txd u i/o evdd k3 aa12 i2c_sda pfeci2c0 ? u2rxd u i/o evdd k4 y12 dma dack1 pdma3 ? ulpi_dir ? o evdd m14 c17 dreq1 pdma2 ? usb_clkin u i evdd p16 c18 dack0 pdma1 dspi_pcs3 ? ? o evdd n15 a18 dreq0 pdma0 ? ? u i evdd n16 b18 dspi dspi_pcs5/pcss pdspi6 ? ? ? o evdd n14 d18 dspi_pcs2 pdspi5 ? ? ? o evdd l13 a19 dspi_pcs1 pdspi4 sbf_cs ? ? o evdd p14 b20 dspi_pcs0/ss pdspi3 ? ? u i/o evdd r16 d17 dspi_sck pdspi2 sbf_ck ? ? i/o evdd r15 a20 dspi_sin pdspi1 sbf_di ? 8 i evdd p15 b19 dspi_sout pdspi0 sbf_do ? ? o evdd n13 c20 table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
pin assignments and reset states mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 13 uarts u1cts puart7 ? ? ? i evdd ? v3 u1rts puart6 ? ? ? o evdd ? u4 u1rxd puart5 ? ? ? i evdd ? p3 u1txd puart4 ? ? ? o evdd ? n3 u0cts puart3 ? ? ? i evdd m3 y16 u0rts puart2 ? ? ? o evdd m2 aa16 u0rxd puart1 ? ? ? i evdd n1 ab16 u0txd puart0 ? ? ? o evdd m1 w15 note: the uart1 and uart 2 signals are multiplexed on the dma timers and i2c pins. dma timers dt3in ptimer3 dt3out u2rxd ? i evdd c13 h2 dt2in ptimer2 dt2out u2txd ? i evdd d13 h1 dt1in ptimer1 dt1out u2cts ? i evdd b14 h3 dt0in ptimer0 dt0out u2rts ? i evdd a15 g1 bdm/jtag 9 pstddata[7:0] ? ? ? ? o evdd e2, d1, f4, e3, d2, c1, e4, d3 aa6, ab6, ab5, w6, y6, aa5, ab4, y5 jtag_en ? ? ? d i evdd m11 c21 pstclk ? tclk ? ? i evdd p13 c22 dsi ? tdi ? u i evdd t15 c19 dso ? tdo ? ? o evdd t14 a21 bkpt ? tms ? u i evdd r14 b21 dsclk ? trst ? u i evdd m13 b22 test test ? ? ? d i evdd m6 ab20 plltest ? ? ? ? o evdd k16 d15 table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
mcf5445x coldfire ? microprocessor data sheet, rev. 2 pin assignments and reset states freescale semiconductor 14 power supplies ivdd ? ? ? ? ? ? e6?12, f5, f12 d6, d8, d14, f4, h4, n4, r4, w4, w7, w8, w12, w16, w19 evdd ? ? ? ? ? ? g5, g12, h5, h12, j5, j12, k5, k12, l5?6, l12 d13, d19, g8, g11, g14, g16, j7, j16, l7, l16, n16, p7, r16, t8, t12, t14, t16 sd_vdd ? ? ? ? ? ? l7?11, m9, m10 f19, h19, k19, m19, r19, u19 vdd_osc ? ? ? ? ? ? l14 b16 vdd_a_pll ? ? ? ? ? ? k15 c14 vdd_rtc ? ? ? ? ? ? m12 c13 vss ? ? ? ? ? ? a1, a16, f6?11, g6?11, h6?11, j6?11, k6?11, t1, t16 a1, a22, b14, g7, g9?10, g12?13, g15, h7, h16, j9?14, k7, k9?14, k16, l9?14, m7, m9?m14, m16, n9?14, p9?14, p16, r7, t7, t9?11, t13, t15, ab1, ab22 vss_osc ? ? ? ? ? ? l15 c16 1 pull-ups are generally only enabled on pins with their primary functi on, except as noted. 2 refers to pin?s primary function. 3 enabled only in oscillator bypass mode (internal crystal oscillator is disabled). 4 serial boot must select 0-bit boot port size to enable the gpio mode on these pins. 5 when the pci is enabled, all pci bus pins come up configured as such. this includes the pci_gnt and pci_req lines, which have gpio. the irq1/pci_inta signal is a special case. it comes up as pci_inta when booting as a pci agent and as gpio when booting as a pci host. for the 360 tepbga, booting with pci disabled results in all dedicated pci pins being safe-stated. the pci_gnt and pci_req lines and irq1/pci_inta come up as gpio. 6 gpio functionality is determined by the edge port module. the pin multiplexing and control module is only responsible for assig ning the alternate functions. 7 depends on programmed polarity of the usb_vbus_oc signal. 8 pull-up when the serial boot fa cility (sbf) controls the pin 9 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the pin multiplexi ng and control module is not responsible for assigning these pins. table 4. mcf5445 x signal information and muxing (continued) signal name gpio alternate 1 alternate 2 pull-up (u) 1 pull-down (d) direction 2 voltage domain mcf54450 MCF54451 256 mapbga mcf54452 mcf54453 mcf54454 mcf54455 360 tepbga
pin assignments and reset states mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 15 4.2 pinout?256 mapbga the pinout for the mcf54450 and MCF54451 packages are shown below. figure 5. mcf54450 and MCF54451 pinout (256 mapbga) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a vss fb_oe fb_ts fb_be/ bwe0 fb_be/ bwe2 fb_ad 2 fb_ad 6 fb_ad 10 fb_ad 14 fb_ad 18 fb_ad 22 fb_ad 26 fb_ad 30 fb_ad 31 t0in vss a b fb_ta fb_r/w usb_ vbus_ oc fb_be/ bwe1 fb_be/ bwe3 fb_ad 3 fb_ad 7 fb_ad 11 fb_ad 15 fb_ad 19 fb_ad 23 fb_ad 27 fb_clk t1in pci_ad 4 pci_ad 6 b c pst ddata2 fb_cs3 fb_cs1 fb_cs0 fb_ad 0 fb_ad 4 fb_ad 8 fb_ad 12 fb_ad 16 fb_ad 20 fb_ad 24 fb_ad 28 t3in pci_ad 3 pci_ad 5 pci_ad 1 c d pst ddata6 pst ddata3 pst ddata0 fb_cs2 fb_ad 1 fb_ad 5 fb_ad 9 fb_ad 13 fb_ad 17 fb_ad 21 fb_ad 25 fb_ad 29 t2in pci_ad 0 pci_ad 2 pci_ad 7 d e fec0_ col pst ddata7 pst ddata4 pst ddata1 usb_ vbus_ en ivdd ivdd ivdd ivdd ivdd ivdd ivdd pci_ad 8 pci_ad 9 pci_ad 10 usb_ dp e f fec0_ crs fec0_ mdio fec0_ mdc pst ddata5 ivdd vss vss vss vss vss vss ivdd pci_ad 11 pci_ad 12 irq_1 usb_ dm f g fec0_ rxclk fec0_ rxdv fec0_ rxd3 fec0_ rxd2 evdd vss vss vss vss vss vss evdd pci_ad 13 pci_ad 14 pci_ad 15 nc g h fec0_ rxd1 fec0_ rxd0 fec0_ rxer fec0_ txclk evdd vss vss vss vss vss vss evdd pci_ad 18 pci_ad 17 pci_ad 16 xtal 32k h j fec0_ txd3 fec0_ txd2 fec0_ txd1 fec0_ txd0 evdd vss vss vss vss vss vss evdd pci_ad 19 pci_ad 20 pci_ad 21 extal 32k j k fec0_ txen fec0_ txer i2c_ scl i2c_ sda evdd vss vss vss vss vss vss evdd pci_ad 22 pci_ad 23 vdd_a _pll pll test k l irq_7 irq_4 irq_3 reset evdd evdd sdvdd sdvdd sdvdd sdvdd sdvdd evdd dspi_ pcs2 vdd_ osc vss_ osc xtal l m u0txd u0rts u0cts sd_a7 boot mod1 test boot mod0 sd_ vref sdvdd sdvdd jtag_ en vdd_ rtc trst dack1 rst out extal m n u0rxd sd_a11 sd_a6 sd_a0 sd_ cke sd_d31 sd_d29 sd_d24 sd_d23 sd_d19 sd_ dqs2 sd_dm2 dspi_ sout dspi_ pcs5 dack0 dreq0 n p sd_a12 sd_a10 sd_a5 sd_ba1 sd_ ras sd_ cs1 sd_d28 sd_d25 sd_ dm3 sd_d20 sd_d16 ssi_fs tclk dspi_ pcs1 dspi_ sin dreq1 p r sd_a13 sd_a9 sd_a4 sd_a1 sd_we sd_ cs0 sd_d27 sd_d26 sd_ dqs3 sd_d21 sd_d17 ssi_txd ssi_ bclk tms dspi_ sck dspi_ pcs0 r t vss sd_a8 sd_a3 sd_a2 sd_ba0 sd_ cas sd_d30 sd_ clk sd_ clk sd_d22 sd_d18 ssi_rxd ssi_ mclk tdo tdi vss t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
mcf5445x coldfire ? microprocessor data sheet, rev. 2 pin assignments and reset states freescale semiconductor 16 4.3 pinout?360 tepbga the pinout for the mcf54452, mcf54453, mcf54454, and mcf54455 packages are shown below. figure 6. mcf54452, mcf54453, mcf54454, and mcf54455 pinout (360 tepbga) 12345678910111213141516171819202122 a gnd pci_ req0 pci_ ad10 pci_ ad11 pci_ ad13 pci_ serr pci_ stop pci_ ad15 pci_ gnt0 pci_ ad29 pci_ ad20 xtal 32k extal 32k usb_ dm usb_ dp extal xtal dack0 dspi_ pcs2 dspi_ sck tdo gnd a b pci_ cbe0 pci_ frame pci_ ad9 pci_ perr pci_ ad12 pci_ rst pci_ gnt3 pci_ ad14 pci_ ad18 pci_ ad28 pci_ ad19 pci_ ad21 nc gnd nc vdd_ osc rst out dreq0 dspi_ sin dspi_ pcs1 tms trst b c pci_ ad0 pci_ ad2 pci_ irdy pci_ pa r pci_ req1 irq1 pci_ req3 pci_ gnt2 pci_ gnt1 pci_ trdy pci_ ad31 pci_ ad22 vdd_ rtc vdd_ a_pll nc vss_ osc dack1 dreq1 tdi dspi_ sout jtag_ en tclk c d pci_ cbe1 pci_ ad1 pci_ ad7 pci_ ad8 pci_ idsel ivdd pci_ req2 ivdd pci_ ad17 pci_ ad16 pci_ ad30 pci_ ad23 evdd ivdd pll test nc dspi_ pcs0 dspi_ pcs5 evdd ssi_ mclk ssi_ rxd ssi_ txd d e pci_ ad4 pci_ ad5 pci_ ad6 pci_ cbe2 ssi_ bclk ssi_fs sd_ dm2 sd_ dqs2 e f pci_ ad24 pci_de vsel pci_ ad3 ivdd sdvdd sd_d16 sd_d17 sd_d18 f g t0in pci_ ad26 pci_ ad25 pci_ cbe3 gnd evdd gnd gnd evdd gnd gnd evdd gnd evdd sd_d19 sd_d20 sd_d21 sd_d22 g h t2in t3in t1in ivdd gnd gnd sdvdd sd_d23 sd_ dm3 sd_ dqs3 h j fb_ad 29 fb_ad 31 fb_clk pci_ ad27 evdd gnd gnd gnd gnd gnd gnd evdd sd_d26 sd_d27 sd_d25 sd_d24 j k fb_ad 28 fb_ad 27 fb_ad 26 fb_ad 30 gnd gnd gnd gnd gnd gnd gnd gnd sdvdd sd_d28 sd_d29 sd_d30 k l fb_ad 25 fb_ad 23 fb_ad 22 fb_ad 24 evdd gnd gnd gnd gnd gnd gnd evdd sd_ cas sd_ cs1 sd_d31 sd_ clk l m fb_ad 21 fb_ad 20 fb_ad 19 fb_ad 18 gnd gnd gnd gnd gnd gnd gnd gnd sdvdd sd_ cs0 sd_ vref sd_ clk m n fb_ad 17 fb_ad 16 u1txd ivdd gnd gnd gnd gnd gnd gnd gnd evdd sd_a2 sd_we sd_ ras sd_ cke n p fb_ad 15 fb_ad 14 u1rxd fb_ad 10 evdd gnd gnd gnd gnd gnd gnd gnd sd_ ba0 sd_a1 sd_a0 sd_ ba1 p r fb_ad 13 fb_ad 12 fb_ad 11 ivdd gnd evdd sdvdd sd_a5 sd_a4 sd_a3 r t fb_ad 9 fb_ad 8 fb_ad 7 fb_ad 6 gnd evdd gnd gnd gnd evdd gnd evdd gnd evdd sd_a9 sd_a8 sd_a7 sd_a6 t u fb_ad 5 fb_ad 4 fb_ad 3 u1rts sdvdd sd_a12 sd_a11 sd_a10 u v fb_ad 2 fb_ad 1 u1cts usb_ vbus_ oc ata _ da2 ata _ da1 ata _ da0 sd_a13 v w fb_ad 0 fb_be/ bwe2 fb_be/ bwe1 ivdd fb_cs3 pst ddata4 ivdd ivdd fec0_ rxd1 fec0_ txd3 fec0_ txen ivdd ata _ reset fec1_ rxclk u0txd ivdd fec1_ rxer fec1_ txd2 ivdd fec1_ mdc ata _ cs1 ata _ cs0 w y fb_be/ bwe3 fb_be/ bwe0 fb_ts fb_cs0 pst ddata0 pst ddata3 fec0_ mdio fec0_ rxdv fec0_ rxd2 fec0_ txclk fec0_ txd0 i2c_ sda ata _ b u ffer_ en ata _ iordy fec1_ rxd2 u0cts fec1_ rxd0 reset fec1_ txd3 fec1_ txd0 nc fec1_ mdio y aa fb_oe usb_ vbus_ en fb_r/w fb_cs2 pst ddata2 pst ddata7 fec0_ crs fec0_ rxclk nc fec0_ rxer fec0_ txd1 i2c_ scl irq4 ata _ dmarq fec1_ rxd3 u0rts fec1_ rxd1 fec1_ crs fec1_ txd1 nc fec1_ txen fec1_ txer aa ab gnd fb_ta fb_cs1 pst ddata1 pst ddata5 pst ddata6 fec0_ col fec0_ mdc fec0_ rxd3 fec0_ rxd0 fec0_ txd2 fec0_ txer irq7 irq3 fec1_ rxdv u0rxd boot mod1 fec1_ col fec1_ txclk test boot mod0 gnd ab 12345678910111213141516171819202122
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 17 5 electrical characteristics this document contains electrical specification tables and re ference timing diagrams for the mcf54455 microprocessor. this section contains detailed informa tion on dc/ac electrical characteristics and ac timing specifications. the electrical specifications are preliminar y and from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cy cle. however, for productio n silicon, these specifications will be met. finalized specifications will be published after co mplete characterization and de vice qualifications have been completed. note the parameters specified in this mcu document supersede any values found in the module specifications. 5.1 absolute maximum ratings table 5. absolute maximum ratings 1, 2 1 functional operating conditions are given in ta b l e 8 . absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. continued operation at these levels may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against damage due to high static voltage or electrical fields. however, it is advised that normal precautions be taken to avoid applicati on of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operat ion is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., v ss or ev dd ). rating symbol pin name value units external i/o pad supply voltage ev dd evdd -0.3 to +4.0 v internal oscillator supply voltage oscv dd vdd_osc -0.3 to +4.0 v real-time clock supply voltage rtcv dd vdd_rtc -0.5 to +2.0 v internal logic supply voltage iv dd ivdd -0.5 to +2.0 v sdram i/o pad supply voltage sdv dd sd_vdd -0.3 to +4.0 v pll supply voltage pv dd vdd_a_pll -0.5 to +2.0 v digital input voltage 3 3 input must be current limited to the value specified. to de termine the value of the required current-limiting resistor, calculate resistance values for positive and negative clam p voltages, and then use the larger of the two values. v in ? -0.3 to +3.6 v instantaneous maximum current single pin limit (applies to all pins) 3, 4, 5 4 all functional non-supply pins are internally clamped to v ss and ev dd . 5 power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ev dd ) is greater than i dd , the injection current may flow out of ev dd and could result in external power supply going out of regulation. ensure the external ev dd load shunts current greater than maximum injection current. this is the greatest risk when the mpu is not consuming power (ex; no clock). the power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. i dd ?25ma operating temperature range (packaged) t a (t l - t h ) ? -40 to +85 c storage temperature range t stg ? -55 to +150 c
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 18 5.2 thermal characteristics the average chip-junction temperature (t j ) in c can be obtained from: eqn. 1 where: t a = ambient temperature, c q jma = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o p int =i dd iv dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approx imate relationship between p d and t j (if p i/o is neglected) is: eqn. 2 solving equations 1 and 2 for k gives: eqn. 3 table 6. thermal characteristics characteristic symbol 256mapbga 360pbga unit junction to ambient, natural convection four layer board (2s2p) ja 29 1,2 1 jma and jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. freescale recommends the use of jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rat ed specification. system des igners should be aware that device junction temperatures can be significantly in fluenced by board layout and surrounding devices. conformance to the device junction temperature specif ication can be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 24 1,2 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 25 1,2 21 1,2 c / w junction to board jb 18 3 3 thermal resistance between the die and the printed circuit board in conformance with jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 15 3 c / w junction to case jc 10 4 4 thermal resistance between the die and the case top su rface as measured by the cold plate method (mil spec-883 method 1012.1). 11 4 c / w junction to top of package jt 2 1,5 5 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51- 2. when greek letters are not availa ble, the thermal characterization parameter is written in conformance with psi-jt. 2 1,5 c / w maximum operating junction temperature t j 105 105 o c t j t a p d jma () + = p d k t j 273 c + () -------------------------------- - = kp d t a 273 c () q jma p d 2 + =
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 19 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 5.3 esd protection 5.4 dc electrical specifications table 7. esd protection characteristics 1, 2 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after ex posure to esd pulses the device no longer meets the device specification requirements. comp lete dc parametric and functional testing is performed per applicable device specificat ion at room temperature followed by hot temperature, unless specified other wise in the device specification. characteristics symbol value units esd target for human body model hbm 2000 v table 8. dc electrical specifications characteristic symbol min max units internal logic supply voltage 1 iv dd 1.35 1.65 v pll analog operation voltage range 1 pv dd 1.35 1.65 v external i/o pad supply voltage ev dd 3.0 3.6 v internal oscillator supply voltage oscv dd 3.0 3.6 v real-time clock supply voltage rtcv dd 1.35 1.65 v sdram i/o pad supply voltage ? ddr mode sdv dd 2.25 2.75 v sdram i/o pad supply voltage ? ddr2 mode sdv dd 1.7 1.9 v sdram i/o pad supply voltage ? mobile ddr mode sdv dd 1.7 1.9 v sdram input reference voltage sdv ref 0.49 x sdv dd 0.51 x sdv dd v input high voltage v ih 0.7 x ev dd 3.65 v input low voltage v il v ss ? 0.3 0.35 x ev dd v input hysteresis v hys 0.06 x ev dd ?mv input leakage current v in = v dd or v ss , input-only pins i in ?1.0 1.0 a high impedance (off-state) leakage current 2 v in = v dd or v ss , all input/output and output pins i oz ?10.0 10.0 a output high voltage (all input/o utput and all output pins) i oh = ?5.0 ma v oh 0.85 ev dd __ v output low voltage (all inpu t/output and all output pins) i ol = 5.0ma v ol __ 0.15 ev dd v
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 20 5.5 clocktiming specifications the clock module configures the device for one of several cloc king methods. clocking modes include internal phase-locked loop (pll) clocking with an external clock reference or an exte rnal crystal reference supported by an internal crystal amplifie r. the pll can also be disabled, and an extern al oscillator can dir ectly clock the device. the specifications in table 9 are for the clkin input pin (extal input driven by an external clock reference). the duty cycle specification is based on an acceptable tole rance for the pll, which yields 50% duty -cycle internal clocks to all on-chip peripherals. the mcf5445 x devices use the input clock signal as its synchr onous bus clock for pci. a poor duty cycle on the input clock, may affect the overall timing ma rgin to external devices. if negative edge logic is used to interface to pci, prov iding a 50% duty-cycle input clock aids in simplifying overall system design. weak internal pull up device current, tested at v il max. 3 i apu ?10 ?130 a input capacitance 4 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf load capacitance low drive strength high drive strength c l 25 50 pf dc injection current 3, 5, 6, 7 v negclamp =v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total mcu limit, includes sum of all stressed pins i ic -1.0 -10 1.0 10 ma 1 iv dd and pv dd should be at the same voltage. pv dd should have a filtered input. plea se see the pll section of this specification for an example circuit. there are three pv dd inputs, one for each pll. a filter circuit should used on each pv dd input. 2 worst-case tristate leakage current with only one i/o pin hi gh. since all i/os share power when high, the leakage current is distributed among them. with all i/os high, this spec reduces to 2 a min/max. 3 refer to the mcf54455 reference manual signals description chapter for pins having weak internal pull-up devices. 4 this parameter is characterized before qualification rather than 100% tested. 5 all functional non-supply pins are internally clamped to v ss and their respective v dd . 6 input must be current limited to the valu e specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clam p voltages, then use the larger of the two values. 7 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if posi tive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure the external v dd load shunts current greater than the maximum injection current. this is the greatest ri sk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low wh ich would reduce overall power consumption. also, at power-up, the system clock is not present during the powe r-up sequence until the pll has attained lock. table 9. input clock timing requirements item specification min max unit c1 cycle time 15 40 ns table 8. dc electrical specifications characteristic symbol min max units
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 21 figure 7. input clock timing diagram 1 / c1 frequency 25 66.66 mhz c2 rise time (20% of vdd to 80% of vdd) - 2 ns c3 fall time (80% of vdd to 20% of vdd) - 2 ns c4 duty cycle (at 50% of vdd) 40 60 % table 10. pll electrical characteristics num characteristic symbol min. value max. value unit 1 pll reference frequency range crystal reference external reference f ref_crystal f ref_ext 16 16 40 66.66 mhz mhz 2 core/system frequency f sys 512 hz 1 266.67 mhz ? core/system clock period t sys ?1/f sys ns 19 vco frequency (f vco = f ref pfdr) f vco 300 540 mhz 3 crystal start-up time 2, 3 t cst ?10ms 4 extal input high voltage crystal mode 4 all other modes (external, limp) v ihext v ihext v xtal + 0.4 e vdd /2 + 0.4 ? ? v v 5 extal input low voltage crystal mode 4 all other modes (external, limp) v ilext v ilext ? ? v xtal - 0.4 e vdd /2 - 0.4 v v 6 extal input rise & fall time (20% to 80% e vdd ) (external, limp) 12ns 7pll lock time 3, 5 t lpll ? 50000 clkin 8 duty cycle of reference 3 (external, limp) t dc 40 60 % 9 xtal current i xtal 13ma 10 total on-chip stray capacitance on xtal c s_xtal ?1.5 pf 11 total on-chip stray capacitance on extal c s_extal ?1.5 pf table 9. input clock timing requirements (continued) item specification min max unit input clock (clkin) c1 c4 c4 c3 c2
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 22 5.6 reset timing specifications table 11 lists specifications for the reset timing parameters shown in figure 8 . 12 crystal capacitive load c l see crystal spec 13 discrete load capacitance for xtal discrete load capacitance for extal c l_xtal c l_extal ?2 (c l - c s_xtal - c s_extal - c s_pcb ) 6 pf 14 frequency un-lock range f ul -4.0 4.0 % f sys 15 frequency lock range f lck -2.0 2.0 % f sys 17 clkout period jitter, 3, 4, 7 measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter c jitter ? ? 10 tbd % fb_clk % fb_clk 1 the minimum system frequency is the minimum input clock divided by the maximum low-power divider (16 mhz 32,768). when the pll is enabled, the minimum system frequency (f sys ) is 150 mhz. 2 this parameter is guaranteed by characterization before qua lification rather than 100% tested. applies to external clock reference only. 3 proper pc board layout procedures must be followed to achieve specifications. 4 this parameter is guaranteed by design rather than 100% tested. 5 this specification is the pll lock time only and does not include oscillator start-up time. 6 c s_pcb is the measured pcb stray capacitance on extal and xtal. 7 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via pll v dd , ev dd , and v ss and variation in crystal oscillator frequency increase the cjitter percentage for a given interval. table 11. reset and configuration override timing num characteristic min max unit r1 1 1 reset and configuration override data lines are synchronized in ternally. setup and hold times must be met only if recognition on a particular clock is required. reset valid to clkin (setup) 9 ? ns r2 clkin to reset invalid (hold) 1.5 ? ns r3 reset valid time 2 2 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. 5 ? clkin cycles r4 clkin to rstout valid ? 10 ns r5 rstout valid to configuration override inputs valid 0 ? ns r6 configuration override inputs valid to rstout invalid (setup) 20 ? clkin cycles r7 configuration override inputs invalid after rstout invalid (hold) 0 ? ns r8 rstout invalid to configuration override inputs high impedance ? 1 clkin cycles table 10. pll electrical characteristics (continued) num characteristic symbol min. value max. value unit
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 23 figure 8. reset and configuration override timing 5.7 flexbus timing specifications a multi-function extern al bus interface called flexbus is pr ovided with basic func tionality to interface to slave-only devices up to a maximum bus frequency of 66mhz. it can be directly conn ected to asynchronous or synchronous devices such as external boot roms, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. for asynchronous devices, a simple chip-s elect based interf ace can be used. all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output cloc k (fb_clk). all other timing relationships can be derived from these values. note the processor drives the da ta lines during the first cl ock cycle of the transfer with the full 32-bit address. this may be ignored by standard connected devices using non-multiplexed addres s and data buses. however, some applications may find th is feature beneficial. the address and data busses are m uxed between the flexbus and pci controller. at the end of the read and write bus cycles the address signals are indeterminate. table 12. flexbus ac timing specifications num characteristic min max unit notes frequency of operation 25 66.66 mhz fb1 clock period 15 40 ns fb2 output valid ? 7.0 ns 1 1 specification is valid fo r all fb_ad[31:0], fb_bs [3:0], fb_cs [3:0], fb_oe , fb_r/w , fb_tbst , fb_tsiz[1:0], and fb_ts . fb3 output hold 1.0 ? ns 1 fb4 input setup 3.0 ? ns 2 2 specification is valid for all fb_ad[31:0] and fb_ta . fb5 input hold 0 ? ns 2 r1 r2 clkin reset rstout r3 r4 r8 r7 r6 r5 configuration overrides*: r4 (bootmod[1:0], override pins])
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 24 figure 9. flexbus read timing figure 10. flexbus write timing fb_clk fb_r/w s0 s1 s2 s3 fb_ale fb_tsiz[1:0] tsiz[1:0] mux?d bus non-mux?d bus fb_a[31:0] fb_d[31: x ] fb_ad[ y :0] fb_ad[31: x ] fb_cs n , fb_oe , fb_be/bwe n fb_ta data data addr[31:0] addr[31: x ] addr[31: x ] addr[ y :0] fb3 fb1 fb2 fb5 fb4 fb5 fb4 fb_clk fb_r/w fb_ale fb_oe s0 s2 s3 data fb_tsiz[1:0] tsiz[1:0] s1 data mux?d bus non-mux?d bus fb_a[31:0] addr[31:0] fb_d[31: x ] addr[31: x ] addr[31: x ] fb_ad[ y :0] fb_ad[31: x ] addr[ y :0] fb_cs n , fb_be/bwe n fb_ta fb3 fb1 fb2 fb5 fb4
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 25 5.8 sdram ac timing characteristics the following timing numbers must be followed to properly latch or drive data onto the sdram memory bus. all timing numbers are relative to the four dqs byte lanes. table 13. sdram timing specifications num characteristic symbol min max unit notes frequency of operation ? 133.33 mhz 1 1 the sdram interface operates at the same frequency as the internal system bus. dd1 clock period t sdck 7.5 ? ns dd2 pulse width high t sdckh 0.45 0.55 t sdck 2 2 pulse width high plus pulse width low cannot exceed min and max clock period. dd3 pulse width low t sdckl 0.45 0.55 t sdck 3 dd4 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] ? output valid t cmv ? (0.5 x t sdck ) + 1.0ns ns 3 3 command output valid should be 1/2 the memory bus clock (t sdck ) plus some minor adjustments for process, temperature, and voltage variations. dd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] ? output hold t cmh 2.0 ? ns dd6 write command to first dqs latching transition t dqss (1.0 x t sdck ) - 0.6ns (1.0 x t sdck ) + 0.6ns ns dd7 data and data mask output setup (dq-->dqs) relative to dqs (ddr write mode) t qs 1.0 ? ns 4 5 4 this specification relates to the required input setup time of ddr memories. the microprocessor?s output setup should be larger than the input setup of the ddr memories. if it is not la rger, then the input setup on the memory is in violation. sd_d[31:24] is relative to sd_dqs[3]; sd_d[23:16] is relative to sd_dqs[2] 5 the first data beat is valid before the firs t rising edge of dqs and after the dqs wr ite preamble. the remaining data beats are valid for each subsequent dqs edge. dd8 data and data mask output hold (dqs-->dq) relative to dqs (ddr write mode) t qh 1.0 ? ns 6 6 this specification relates to the required hold time of ddr memories. sd_d[31:24] is relative to sd_dqs[3]; sd_d[23:16] is relative to sd_dqs[2] dd9 input data skew relative to dqs (input setup) t is ?1.0ns 7 7 data input skew is derived from each dqs clock edge. it begi ns with a dqs transition and ends when the last data line becomes valid. this input skew must in clude ddr memory output skew a nd system level board skew (due to routing or other factors). dd10 input data hold relative to dqs. t ih (0.25 x t sdck ) + 0.5ns ?ns 8 8 data input hold is derived from each dqs clock edge. it begins with a dqs transition and ends when the first data line becomes invalid.
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 26 figure 11. ddr write timing sd_clk sd_cs n ,sd_we , sd_dm3/sd_dm2 sd_d[31:24]/sd_d[23:16] sd_a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs3/sd_dqs2 dd8 dd8 dd7 sd_clk dd3 dd2 dd6
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 27 figure 12. ddr read timing 5.9 pci bus timing specifications the pci bus on the device is pci 2.2 compliant. the following timing numbers are mostly from the pci 2.2 spec. refer to the pci 2.2 spec for a more detailed timing analysis. table 14. pci timing specifications 1 , 2 num characteristic 33 mhz 3 66 mhz 3 min max min max unit frequency of operation ? 33.33 33.33 66.66 mhz p1 clock period 30 ? 15 30 ns p2 bused pci signals ? input setup 7.0 ? 3.0 ? ns p3 pci_gnt [3:0]/pci_req [3:0] ? input setup 10.0 ? 5.0 ? ns p4 all pci signals ? input hold 0 ? 0 ? ns p5 bused pci signals ? output valid ? 11.0 ? 6.0 ns sd_clk sd_cs n ,sd_we , sd_dqs3/sd_dqs2 d[31:24]/d[23:16] sd_a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 wd1wd2wd3wd4 sd_dqs3/sd_dqs2 dd9 sd_clk dd3 dd2 d[31:24]/d[23:16] wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 28 figure 13. pci timing 5.9.1 overshoot and undershoot figure 14 shows the specification limits for overshoot and undershoot for pci i/o. to guarantee long term reliability, the specification limits shown must be followed. good transmission line design practices should be observed to guarantee the specification limits. p6 pci_req [3:0]/pci_gnt [3:0] ? output valid ? 12.0 ? 6.0 ns p7 all pci signals ? output hold 2.0 ? 1.0 ? ns 1 the pci bus operates at the clkin frequency. all timings are relative to the input clock, clkin. 2 all pci signals are bused signals except for pci_gnt[3:0] a nd pci_req[3:0]. these signals are defined as point-to-point signals by the pci specification. 3 the 66-mhz parameters are only guaranteed when the 66-mhz pci pad slew rates are selected. likewise, the 33-mhz parameters are only guaranteed when the 33-mhz pci pad slew rates are selected. table 14. pci timing specifications 1 , 2 (continued) num characteristic 33 mhz 3 66 mhz 3 min max min max unit clkin input setup/hold p1 p7 p4 output valid input valid output valid/hold p5 p6 p2 p3
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 29 figure 14. overshoot and undershoot limits 5.10 ulpi timing specifications the ulpi interface is fully compliant wi th the industry standard utmi+ low pin interface. contro l and data timing requirements for the ul pi pins are given in table 15 . these timings apply to synchronous mode only. all timings are measured with respect to the clock as seen at the usb_clkin pin on the mcf5445 x . the ulpi phy is the source of the 60mhz clock. note the usb controller requires a 60-mhz clock, even if using the on-chip fs/ls transceiver instead of the ulpi interface. in this case, the 60-mhz clock can be generated by the pll or input on the usb_clkin pin. table 15. ulpi interface timing num characteristic min nominal max units usb_clkin operating frequency ? 60 ? mhz usb_clkin duty cycle ? 50 ? % u1 usb_clkin clock period ? 16.67 ? ns u2 input setup (control and data) 5.0 ? ? ns u3 input hold (control and data) 1.0 ? ? ns u4 output valid (control and data) ? ? 9.5 ns u5 output hold (control and data) 1.0 ? ? not to exceed 17% of pci cycle v dd + 0.9v v dd + 0.5v v dd gnd - 1.0v gnd - 0.5v gnd
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 30 figure 15. ulpi timing diagram 5.11 ssi timing specifications this section provides the ac timings for th e ssi in master (clocks driven) and slave modes (clocks input). all timings are give n for non-inverted serial clock polarity (ssi_tcr[tsckp] = 0, ss i_rcr[rsckp] = 0) and a n on-inverted frame sync (ssi_tcr[tfsi] = 0, ssi_rcr[rfsi] = 0). if th e polarity of the clock and/ or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (ssi_bclk) and/ or the frame sync (ssi_fs) shown in the figures below. table 16. ssi timing ? master modes 1 1 all timings specified with a capactive load of 25pf. num description symbol min max units notes s1 ssi_mclk cycle time t mclk 2 t sys ?ns 2 2 ssi_mclk can be generated from ssi_clkin or a di vided version of the internal system clock (f sys ). s2 ssi_mclk pulse width high / low 45% 55% t mclk s3 ssi_bclk cycle time t bclk 8 t sys ?ns 3 3 ssi_bclk can be derived from ssi_clkin or a di vided version of the internal system clock (f sys ). s4 ssi_bclk pulse width 45% 55% t bclk s5 ssi_bclk to ssi_fs output valid ? 15 ns s6 ssi_bclk to ssi_fs output invalid 0 ? ns s7 ssi_bclk to ssi_txd valid ? 15 ns s8 ssi_bclk to ssi_txd invalid / high impedence -2 ? ns s9 ssi_rxd / ssi_fs input se tup before ssi_bclk 10 ? ns s10 ssi_rxd / ssi_fs input hold after ssi_bclk 0 ? ns ulpi_data[7:0] (data output) ulpi_data[7:0] (data input) ulpi_dir / ulpi_nxt (control input) ulpi_stp (control output) usb_clkin u1 u2 u2 u3 u3 u4 u4 u5 u5
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 31 figure 16. ssi timing ? master modes table 17. ssi timing ? slave modes 1 1 all timings specified with a capactive load of 25pf. num description symbol min max units notes s11 ssi_bclk cycle time t bclk 8 t sys ?ns s12 ssi_bclk pulse width high / low 45% 55% t bclk s13 ssi_fs input setup before ssi_bclk 10 ? ns s14 ssi_fs input hold after ssi_bclk 2 ? ns s15 ssi_bclk to ssi_txd / ssi_fs output valid ? 15 ns s16 ssi_bclk to ssi_txd / ssi _fs output invalid / high impedence 0? ns s17 ssi_rxd setup before ssi_bclk 10 ? ns s18 ssi_rxd hold after ssi_bclk 2 ? ns ssi_mclk (output) ssi_bclk (output) ssi_fs (output) ssi_txd ssi_rxd s1 s2 s2 s3 s4 s4 s5 s6 s7 s8 s8 s9 s10 s7 ssi_fs (input) s9 s10
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 32 figure 17. ssi timing ? slave modes 5.12 i 2 c timing specifications table 18 lists specifications for the i 2 c input timing parameters shown in figure 18 . table 19 lists specifications for the i 2 c output timing parameters shown in figure 18 . table 18. i 2 c input timing specifications between scl and sda num characteristic min max units i1 start condition hold time 2 ? t sys i2 clock low period 8 ? t sys i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il =0.5 v) ? 1 ms i6 clock high time 4 ? t sys i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? t sys i9 stop condition setup time 2 ? t sys table 19. i 2 c output timing specificat ions between scl and sda num characteristic min max units i1 1 start condition hold time 6 ? t sys i2 1 clock low period 10 ? t sys i3 2 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih =2.4 v) ? ? s i4 1 data hold time 7 ? t sys i5 3 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns ssi_bclk (input) ssi_fs (input) ssi_txd ssi_rxd s11 s12 s12 s14 s15 s16 s16 s17 s18 s15 s13 ssi_fs (output) s15 s16
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 33 figure 18. i 2 c input/output timings 5.13 fast ethernet timing specifications the following timing specs are defined at the chip i/o pin and must be translated appropriatel y to arrive at timing specs/constraints for th e physical interface. 5.13.1 receive signal timing specifications the following timing specs meet the requir ements for mii and 7-wire style interf aces for a range of transceiver devices. i6 1 clock high time 10 ? t sys i7 1 data setup time 2 ? t sys i8 1 start condition setup time (for repeated start condition only) 20 ? t sys i9 1 stop condition setup time 10 ? t sys 1 output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 1 9 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division va lues programmed into the ifdr. however, the numbers given in ta b l e 1 9 are minimum values. 2 because i2c_scl and i2c_sda are open-collector-type ou tputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 specified at a nominal 50-pf load. table 20. receive signal timing num characteristic mii mode rmii mode unit min max min max ? rxclk frequency ? 25 ? 50 mhz e1 rxd[n:0], rxdv, rxer to rxclk setup 1 1 in mii mode, n = 3; in rmii mode, n = 1 5?4? ns e2 rxclk to rxd[n:0], rxdv, rxer hold 1 5?2? ns e3 rxclk pulse width high 35% 65% 35% 65% rxclk period e4 rxclk pulse width low 35% 65% 35% 65% rxclk period table 19. i 2 c output timing specifications between scl and sda (continued) num characteristic min max units i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 34 figure 19. mii receive signal timing diagram 5.13.2 transmit signal timing specifications figure 20. mii transmit signal timing diagram 5.13.3 asynchronous input signal timing specifications table 21. transmit signal timing num characteristic mii mode rmii mode unit min max min max ? txclk frequency ? 25 ? 50 mhz e5 txclk to txd[n:0], txen, txer invalid 1 1 in mii mode, n = 3; in rmii mode, n = 1 5?5? ns e6 txclk to txd[n:0 ], txen, txer valid 1 ? 25 ? 14 ns e7 txclk pulse width high 35% 65% 35% 65% t txclk e8 txclk pulse width low 35% 65% 35% 65% t txclk table 22. mii transmit signal timing num characteristic min max unit e9 crs, col minimum pulse width 1.5 ? txclk period valid data rxclk (input) rxd[n:0] rxdv, rxer e3 e4 e1 e2 valid data txclk (input) txd[n:0] txen, txer e7 e8 e5 e6
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 35 figure 21. mii async inputs timing diagram 5.13.4 mii serial management timing specifications figure 22. mii serial management channel timing diagram 5.14 32-bit timer module timing specifications table 24 lists timer module ac timings. table 23. mii serial management channel signal timing num characteristic symbol min max unit e10 mdc cycle time t mdc 400 ? ns e11 mdc pulse width 40 60 % t mdc e12 mdc to mdio output valid ? 375 ns e13 mdc to mdio output invalid 25 ? ns e14 mdio input to mdc setup 10 ? ns e15 mdio input to mdc hold 0 ? ns table 24. timer module ac timing specifications name characteristic min max unit t1 dt n in cycle time ( n =0:3) 3 ? t sys/2 t2 dt n in pulse width ( n =0:3) 1 ? t sys/2 crs, col e9 mdc (output) e11 mdio (output) mdio (input) e11 e12 e13 valid data e14 e15 valid data e10
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 36 5.15 ata interface timing specifications the ata controller is compatible with the ata/atapi-6 industry standard. refer to the ata/atapi-6 specficiation and the ata controller chapter of the mcf54455 reference manual for timing diagrams of the various modes of operation. the timings of the various ata data transfer modes are determin ed by a set of timing equations described in the ata section of the mcf54455 reference manual . these timing equations must be fulfilled for the ata host to meet timing. table 25 provides implementation specific ti ming parameters necessary to complete the timing equations. 5.16 dspi timing specifications the dma serial peripheral interface (dspi) provides a synchronou s serial bus with master and slave operations. many of the transfer attributes are programmable. table 26 provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the mcf54455 reference manual for information on the modified tran sfer formats used for communicating with slower peripheral devices. table 25. ata interface timing specifications 1,2 1 these parameters are guaranteed by design and not testable. 2 all timings specified with a capacitive load of 40pf. name characteristic symbol min max unit notes a1 setup time ? ata_iordy to sysclk falling t sui 4.0 ? ns a2 hold time ? ata_iordy from sysclk falling t hi 3.0 ? ns a3 setup time ? ata_data[15:0] to sysclk rising t su 4.0 ? ns a4 propagation delay ? sysclk rising to all outputs t co ?7.0ns 3 3 applies to ata_cs [1:0], ata_da[2:0], ata_dior, ata_ diow, ata_dmack, ata_data[15:0] a5 output skew t skew1 ?1.5ns 3 a6 setup time ? ata_data[15:0] valid to ata_iordy t i_ds 2.0 ? ns 4 4 applies to ultra dma data-in burst only a7 hold time ? ata_iordy to ata_data[15:0] invalid t i_dh 3.5 ? ns 4 table 26. dspi module ac timing specifications 1 name characteristic symbol min max unit notes ds1 dspi_sck cycle time t sck 4 x t sys ?ns 2 ds2 dspi_sck duty cycle ? (t sck 2) - 2.0 (t sck 2) + 2.0 ns 3 master mode ds3 dspi_pcs n to dspi_sck delay t csc (2 t sys ) - 1.5 ? ns 4 ds4 dspi_sck to dspi_pcs n delay t asc (2 t sys ) - 3.0 ? ns 5 ds5 dspi_sck to dspi_sout valid ? ? 5 ns ds6 dspi_sck to dspi_sout invalid ? -5 ? ns ds7 dspi_sin to dspi_sck input setup ? 9 ? ns ds8 dspi_sck to dspi_sin input hold ? 0 ? ns slave mode ds9 dspi_sck to dspi_sout valid ? ? 10 ns
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 37 figure 23. dspi classic spi timing ? master mode ds10 dspi_sck to dspi_sout invalid ? 0 ? ns ds11 dspi_sin to dspi_sck input setup ? 2 ? ns ds12 dspi_sck to dspi_sin input hold ? 7 ? ns ds13 dspi_ss active to dspi_sout driven ? ? 10 ns ds14 dspi_ss inactive to dspi_sout not driven ? ? 10 ns 1 timings shown are for dmcr[mtfe] = 0 (classic spi) and dctar n [cpha] = 0. data is sampled on the dspi_sin pin on the odd-numbered dspi_sck edges and driven on the dspi_sout pin on even-numbered dspi edges. 2 when in master mode, the baud rate is programmable in dctar n [dbr], dctar n [pbr], and dctar n [br]. 3 this specification assu mes a 50/50 duty cycle setting. the duty cycle is programmable in dctar n [dbr], dctar n [cpha], and dctar n [pbr]. 4 the dspi_pcs n to dspi_sck delay is programmable in dctar n [pcssck] and dctar n [cssck]. 5 the dspi_sck to dspi_pcs n delay is programmable in dctar n [pasc] and dctar n [asc]. table 26. dspi module ac timing specifications 1 (continued) name characteristic symbol min max unit notes dspi_pcs n dspi_sck dspi_sout dspi_sin dspi_sck (dctarn[cpol] = 1) (dctarn[cpol] = 0) data last data first data first data data last data ds1 ds2 ds2 ds3 ds4 ds5 ds6 ds7 ds8
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 38 figure 24. dspi classic spi timing ? slave mode 5.17 sbf timing specifications the serial boot facility (sbf) provides a means to read confi guration information and system boo t code from a broad array of spi-compatible eeproms, flashes, frams, nvsrams, etc. table 27 provides the ac timing specifications for the sbf. table 27. sbf ac timing specifications name characteristic symbol min max unit notes sb1 sbf_ck cycle time t sbfck 40 ? ns 1 1 at reset, the sbf_ck cycle time is t ref 67. the first byte of data read from t he serial memory contains a divider value that is used to set the sbf _ck cycle time for the duration of the serial boot process. sb2 sbf_ck high/low time ? 30% ? t sbfck sb3 sbf_cs to sbf_ck delay ? t sbfck - 2.0 ? ns sb4 sbf_ck to sbf_cs delay ? t sbfck - 2.0 ? ns sb5 sbf_ck to sbf_do valid ? -5 ? ns sb6 sbf_ck to sbf_do invalid ? 5 ? ns sb7 sbf_di to sbf_sck input setup ? 10 ? ns sb8 sbf_ck to sbf_d i input hold ? 0 ? ns dspi_ss dspi_sck dspi_sout dspi_sin dspi_sck (dctarn[cpol] = 1) (dctarn[cpol] = 0) last data first data data data first data last data ds1 ds2 ds2 ds9 ds10 ds11 ds12 ds13 ds14
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 39 figure 25. sbf timing 5.18 general purpose i/o timing specifications figure 26. gpio timing table 28. gpio timing 1 1 these general purpose specifications apply to the following signals: irq n , all uart signals, all timer signals, dack n and dreq n , and all signals configured as gpio. num characteristic min max unit g1 fb_clk high to gpio output valid ? 9 ns g2 fb_clk high to gpio output invalid 1.5 ? ns g3 gpio input valid to fb_clk high 9 ? ns g4 fb_clk high to gpio input invalid 1.5 ? ns sbf_cs sbf_do sbf_di data last data first data first data data last data sb3 sb4 sb5 sb6 sbf_ck sb1 sb2 sb2 sb7 sb8 g1 fb_clk gpio outputs g2 g3 g4 gpio inputs
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 40 5.19 jtag and boundary scan timing figure 27. test clock input timing table 29. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. henc e, specific timing is not associated with it. min max unit j1 tclk frequency of operation dc 20 mhz j2 tclk cycle period 50 ? ns j3 tclk clock pulse width 20 30 ns j4 tclk rise and fall times ? 3 ns j5 boundary scan input data setup time to tclk rise 5 ? ns j6 boundary scan input data hold time after tclk rise 20 ? ns j7 tclk low to boundary scan output data valid ? 33 ns j8 tclk low to boundary scan output high z ? 33 ns j9 tms, tdi input data setu p time to tclk rise 4 ? ns j10 tms, tdi input data hold time after tclk rise 10 ? ns j11 tclk low to tdo data valid ? 11 ns j12 tclk low to tdo high z ? 11 ns j13 trst assert time 50 ? ns j14 trst setup time (negation) to tclk high 10 ? ns tclk v il v ih j4 j4 (input) j2 j3 j3
electrical characteristics mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 41 figure 28. boundary scan (jtag) timing figure 29. test access port timing figure 30. trst timing input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j7 j8 j7 j6 j5 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j13 j14
mcf5445x coldfire ? microprocessor data sheet, rev. 2 electrical characteristics freescale semiconductor 42 5.20 debug ac timing specifications table 30 lists specifications for the debug ac timing parameters shown in figure 31 and table 32 . figure 31. real-time trace ac timing figure 32. bdm serial port ac timing table 30. debug ac timing specification num characteristic min max units d0 pstclk cycle time 1 1 t sys d1 pstclk rising to pstddata valid ? 3.0 ns d2 pstclk rising to pstddata invalid 1.5 ? ns d3 dsi-to-dsclk setup 1 ? pstclk d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of pstclk. dsclk-to-dso hold 4 ? pstclk d5 dsclk cycle time 5 ? pstclk d6 bkpt assertion time 1 ? pstclk pstclk pstddata[7:0] d0 d1 d2 past current dsclk dsi dso next current d5 d3 d4
power consumption mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 43 6 power consumption all power consumption data is lab data measured on an m54455evb running the freescale linux bsp. figure 33. power consumption in various applications table 31. mcf4455 application power consumption 1 1 all voltage rails at nominal values: iv dd = 1.5 v, ev dd = 3.3 v, and sdv dd = 1.8 v. core freq. idle mp3 playback tftp download usb hs file copy units 266 mhz iv dd 215.6 288.8 274.4 263.7 ma ev dd 27.6 33.6 32.6 32.4 sdv dd 142.9 158.2 161.1 158.0 total power 672 829 809 787 mw 200 mhz iv dd 163.8 228.0 213.8 207.9 ma ev dd 29.9 34.7 34.3 33.8 sdv dd 142.2 158.5 160.0 153.4 total power 601 742 722 699 mw 500 550 600 650 700 750 800 850 idle mp3 playback tftp download usb hs file copy total power (mw) 266 mhz 200 mhz
mcf5445x coldfire ? microprocessor data sheet, rev. 2 power consumption freescale semiconductor 44 all current consumption data is lab data measured on a single device using an evaluation board. table 32 shows the typical power consumption in low-power modes. these current m easurements are taken after executing a stop instruction. table 32. current consumption in low-power modes 1,2 1 all values are measured on an m54455evb with 1.5v iv dd power supply. tests performed at room temperature. 2 refer to the power management chapter in the mcf54455 reference manual for more information on low-power modes. mode voltage supply system frequency 166 (typ) 3 3 all peripheral clocks are off except uart0, intc0, iack, edge port, reset controller, ccm, pll, and flexbus prior to entering low-power mode. 200 (typ) 3 233 (typ) 3 266 (typ) 3 266 (peak) 4 4 all peripheral clocks on prior to entering low-power mode. run iv dd (ma) 93.4 110.9 128.2 145.4 202.1 power (mw) 140.1 166.3 192.4 218.1 303.2 wait/doze iv dd (ma) 28.0 32.7 37.5 41.1 100.2 power (mw) 42.0 49.1 56.2 61.7 150.3 stop 0 iv dd (ma) 17.1 19.8 22.5 25.2 25.2 power (mw) 25.7 29.7 33.7 37.8 37.8 stop 1 iv dd (ma) 17.9 19.8 22.4 25.1 25.1 power (mw) 26.8 29.6 33.6 37.6 37.6 stop 2 iv dd (ma)5.75.75.75.75.7 power (mw) 8.6 8.6 8.6 8.6 8.6 stop 3 iv dd (ma)1.81.81.81.81.8 power (mw) 2.6 2.6 2.6 2.6 2.6
package information mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 45 figure 34. iv dd power consumption in low-power modes 7 package information the latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire . table 33 lists the case outline numbers per device. use these numbers in the web page?s keyword search engine to find the latest package outline drawings. 8 product documentation documentation is available from a local freescale distributor, a freescale sales office, the fr eescale literature distribution center, or through the freescal e world-wide web address at http://www.freescale.com/coldfire . table 33. package information device package type case outline numbers mcf54450 256 mapbga 98arh98219a MCF54451 mcf54452 360 tepbga 98are10605d mcf54453 mcf54454 mcf54455 0.0 25.0 50.0 75.0 100.0 125.0 150.0 175.0 200.0 225.0 250.0 275.0 300.0 325.0 166 200 233 266 266 (peak) system frequency (mhz) iv dd power consumption (mw) run wait/doze stop 0 stop 1 stop 2 stop 3
mcf5445x coldfire ? microprocessor data sheet, rev. 2 revision history freescale semiconductor 46 9 revision history table 34 summarizes revisions to this document. table 34. revision history rev. no. date summary of changes 0 sept 17, 2007 initial public release. 1 feb 15, 2008 corrected vss pi n locations in mcf5445 x signal information and muxing table for the 360 tepbga package: changed ?...m9, m16, m17...? to ?...m9?m14, m16...? updated flexbus read and write timing diagrams and added two notes before them. change fb_a[23:0] to fb_a[31:0] in fl exbus read and write timing diagrams. added power consumption section. 2 may 1, 2008 in family configurations table, added pci as feature on 256-pin devices. on these devices the pci_ad bus is limited to 24-bits. in absolute maximum ratings table, changed rtcv dd specification from ?-0.3 to +4.0? to ?-0.5 to +2.0?. in dc electrical specifications table: ? changed rtcv dd specification from 3.0?3.6 to 1.35?1.65. ? changed high impedance (off-s tate) leakage current (i oz ) specification from 1 to 10 a, and added footnote to this spec: ?worst-case tristate leakage current with only one i/o pin high. since all i/os share power when high, the leakage curren t is distributed among them. with all i/os high, this spec reduces to 2 a min/max.?
revision history mcf5445x coldfire ? microprocessor data sheet, rev. 2 freescale semiconductor 47
document number: mcf54455 rev. 2 05/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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